Indexer64 Design Documentation

This document supplements the schematics for the Xilinx-Based Indexer64 Board. You should refer to the design specifications for a description of the board's functionality. What follows is specific to this implementation.

The natural organization is the organization of the drawings themselves:

                     IDX_BD
                       |
                 +-----+----+
                 |          |
              IDX_BUF     XXIDX
                            |
                 +----------+-------------------+
               SBIF       GCLKS              IDXCHAN
                 |                              |
           +----------+         +---------+----------+-------+
           |          |         |         |          |       |
         SDBIF     IREQBIT    LIMITS    STEPCLK    CTRS   RATEGEN
           |                                         |
         IOBITA                                   CTSTATE

IDX_BD

This is the top-level schematic for the board. As shown, it supports two Xilinx chips, each driving three buffers for a total of six indexer channels. Many of these numbers are arbitrary until the design is finalized. The internal design of the Xilinx circuit could support up to seven channels in one chip without redesign if the chip were large enough. We would hope to get at least five channels on a board in order to meet the needs of current experiments.

IDX_BUF

This drawing is separated from IDX_BD simply to make the buffer circuit drawing smaller. For each indexer channel, there are three outputs (SO, DO and RO) and five inputs (LA, LB, ZR, SA and SB).

XXIDX

This is the top-level schematic for the Xilinx chip, consisting of two (or possibly more) sheets (XXIDX.1, XXIDX.2, ...). The circuit on the top of the first sheet depicts all of the pad I/O to the subbus. This includes the address bus, the data bus, the control lines (EXPRD, EXPWR and CMDENBL) and the interrupt and acknowledge lines. The details of this interface is encapsulated in the SBIF schematic, described below.

The next section provides broad address decoding of the buffered address bus. The topmost fork provides the decode for individual channels within the chip. The second fork provides the decode for all addresses on the board. The signal BDSEL is true when anything on the board (chip) is being addressed. Address blocks starting at 0xA00, 0xA40, 0xA80 or 0xAC0 can be selected by use of the off-chip jumpers, JP0 and JP1.

At the bottom of this sheet is the GCLKS part, which simply needs to be referenced in a top-level drawing.

On the second sheet (and following sheets if necessary) are the interfaces to the individual channels. The details of the channel design are found in the IDXCHAN drawings.

At the bottom of this sheet are circuits pertaining to the channels' interrupts. All the channels drive a common open-drain signal, SVC_NOT, when they require service. This is pulled up here and inverted to provide the IREQ signal, which is passed to the SBIF part back on XXIDX.1.

When an interrupt is serviced, the driver software will want to determine which channels require service. Toward this end, the RUNNING output of each channel is fed to different data bit: Channel 1 is connected to D0, Channel 2 is connected to D1, etc. These are enabled onto the data bus when a subbus read from the boards base address is performed. (CE0 and RD).

SBIF

SBIF stands for "Subbus Interface". This provides all the details required to interface the board to the subbus cable.

The topmost circuit on this page provides the address decode for interrupt acknowledge (INTA). The address for INTA is determined by a globally defined base address (0x04X) and two software configuration bits (ICP3 and ICP4). The resulting addresses are shown in the specification. ICP5 is also used here to enable or disable interrupts completely. The top-right and-gate enforces the requirement that no board should assert an interrupt during any interrupt acknowledge cycle.

The circuit nested below the INTA circuit shows the interface to the SDBIF circuit.

Below that, is the data register which holds the Interrupt Configuration, or ICP bits.

To the right is the IREQBIT part, described later.

Next below these comes a circuit to select which data line to drive during an interrupt acknowledge cycle. The BITEN vector will contain one asserted line during INTA, and all the lines will be asserted during all other reads from this board.

The bottom-most circuit is the standard EXPACK implementation with the additional complexity of acknowledging an interrupt acknowledge.

SDBIF

SDBIF provides the functionality of an inverting transceiver for the data bus together with the ability to drive a single software-selectable bit on the data bus to service interrupt acknowledges.

IOBITA

This is the bit-level inverting transceiver function.

GCLKS

GCLKS provides five global clock signals for use within the channels. F8M is used to clock various state machines. The others are all divided down from F16K and are passed to the RATEGEN part within each channel.

IREQBIT

IREQBIT simply drives the current value of the IREQ signal onto all of the low-order internal data bus lines during an INTA cycle. Not all of these bits reach the external subbus data bus, since only one data bit is enabled onto the external bus during INTA.

IDXCHAN

IDXCHAN is the top level of the individual indexer channel. The drawing is divided onto three sheets (IDXCHAN.1, IDXCHAN.2 and IDXCHAN.3).

The first sheet provides a general overview of how the channel operates. The RATEGEN part provides a step rate. LIMITS, together with CMDENBL and the ZEROCT determines whether stepping can proceed. STEPCLK generates the RUNNING and STEP outputs, and the STEP is passed on to the CTRS for recording.

The polarity of the three main outputs, STEPOUT, RUNOUT and DIROUT, are controlled via configuration port bits CP2-4, specified in the channel configuration.

At the top of the second sheet is the definition of the channel's status port, as defined in the specification.

The bottom half of that sheet has the implementation of a state machine which controls this channel's interrupt. The two state variables define whether an interrupt has been requested and whether it has been serviced respectively. Once an interrupt has been serviced, another will not be asserted until the channel is driven again. This circuit was implemented by hand-translating this state diagram into a truth table and its karno maps.

The third sheet, IDXCHAN.3 holds the two pieces of the channel's configuration port. The low five bits define crucial channel configuration, while the upper bits determine the channel's step rate.

The low configuration bits are only updated if bit 5 of the data word is set, allowing the step rate configuration to be set without modifying the basic configuration.

LIMITS

The limits module is charged with the configuration and monitoring of the channel's limit switches and zero reference. Configuration bit CP0 determines which of the limit switches is the InLimit and which is the OutLimit. The LIMIT output is true if the limit which corresponds to the direction of travel has been asserted. Flip-flops have been added to provide debouncing; while driving in, if the InLimit is observed, LIMIT will be asserted and remain asserted until the direction of travel is changed.

The second sheet contains the zero-reference reset state machine. Configuration bit CP1 determines whether or not there is a physical zero reference signal. If not, the InLimit itself is used. This circuit was also generated from a truth table and karno maps.

STEPCLK

Stepclk is a simple circuit with two inputs and two outputs. RCLK is the running rate clock produced from the RATEGEN circuit. STEPENBL is high when the channel should be stepping. STEPCLK is the qualified step output which is sent to the drive and the counters. RUNNING is set high for the duration of a drive, bracketing all of the STEPCLK pulses.

RATEGEN

This circuit generates the channel's step rate by selecting one of the four global clock rates (F1-F4) and passing the result through two optional divide-down circuits. The first is a divide by 2, the second a divide by 3/2. Either circuit can be used or bypassed independently based on one of the rate configuration bits. The entire table of available rates is listed in the specification.

CTRS

The Ctrs circuit contains two 16-bit the counters. The first is an up/down counter which records and reports the channel's current position. The second is an up-counter for defining the length of a drive. Both counters can be preset by software. Ordinarily, the position counter is preset only during initialization, whereas the drive counter is programmed for each drive sequence.

The RESETPOS input provides an asynchronous clear of the position counter. The signal comes from the Limits circuit and is used to tie the drive's position to the hardware In Limit and/or the Zero Reference signals.

The intricacies of setting the counters are goverened by the CTSTATE circuit.

ZEROCT is the terminal count output of the drive counter. Hence, when it is asserted, stepping should be disabled. Terminal count outputs are known to be glitchy, but we are protected from those glitches by the fact that we sample the resulting value synchronously within the STEPCLK part.

CTSTATE

CTSTATE.1 is the implementation of a state machine to handle counting and presetting for the two counters. The reason this function is so complicated is that both increment and load functions use the same clock. We obviously need to disable counting while loading and vice versa.

CTSTATE.2 is the state diagram for the same circuit. The two horizontal paths represent load sequences. The two vertical paths represent stop sequences. I use a notational shortcut here to represent the present state; I specify an 'x' to indicate "don't care" or "either" as a destination and "both" as a source. In the truth table, a next state of 'x' indicates I don't care what that channel goes to; when translating an 'x' in the present state, I make two entries in the truth table, one for x=0 and one for x=1.

I generated the circuite in CTSTATE.1 by hand-translating the state diagram into truth tables and karno maps, then writing the equations for the D flip-flops.