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Xilinx-Based Indexer64 Specification

0.0: Contents

1.0: Summary

The purpose of this document is to specify the functions required for the Indxr64 Stepper-Motor Indexer board.

The primary function of the Indxr64 is to provide step and direction outputs to stepper-motor driver circuitry while allowing for asynchronous status queries from the computer.

Indxr64 is intended to connect to the Subbus64 stack and interface to the motor drivers via (TBD) connectors.

2.0: Basic Configuration

The Base Address of the indexer board is configured with the two jumpers JP0 and JP1 according to the following table: 
        JP0  JP1  Base Address
        Off  Off      A00
         On  Off      A40
        Off   On      A80
         On   On      AC0
This allows address space for up to 7 channels per board, assuming that will meet or exceed the capacity of the Xilinx chip. The addresses of the individual channels are located at an offset from the Base Address: 
        Offset  Function
          0     W: Interrupt Configuration Port
                R: Board Status Port
          8     Channel 1 Base Address
         10     Channel 2 Base Address
         18     Channel 3 Base Address
         20     Channel 4 Base Address
         28     Channel 5 Base Address
         30     Channel 6 Base Address
         38     Channel 7 Base Address
The interrupt configuration port (ICP) is a 6-bit register programmed by writing a value to the board's base address. The 6 low-order bits of the data value written (bits 0 through 5) determine how the board handles interrupt requests.

ICP bit 5 is the interrupt enable bit. If it is zero, no interrupts will be asserted by the board and no interrupts will be acknowledged by the board.

ICP bits 3 and 4 determine which interrupt acknowledge address the board will respond to (assuming ICP5 is set). 

        ICP4  ICP3  Interrupt Acknowledge Address
          0     0       40
          0     1       42
          1     0       44
          1     1       46
Multiple Interrupt Acknowledge Addresses are required to provide interrupt support for different sections of backplane separated by repeaters.

ICP bits 0-2 indicate which data bit this board will drive during an interrupt acknowledge (INTA). Each board requiring interrupt service must be assigned a unique combination of interrupt acknowledge address and interrupt data bit. Furthermore, all boards using a particular interrupt acknowledge address must be located on the same segment of backplane (or cable) since the operation of repeaters defeats the single-bit technique used here.

An interrupt acknowledge cycle (INTA) consists of a read from one of the interrupt acknowledge addresses. During INTA, the board must discontinue asserting the interrupt. This is a technique we arrived at after working with the Timer Board for several years. By requiring that the interrupt be deasserted during INTA, we guarantee that any interrupts which were not recognized by the current interrupt will be recognized as new interrupts.

Reading from the board's base address returns a status word indicating the current status of each channel. Bit 0 is the status of channel 1, Bit 1 is the status of channel 2 and so on. The bit is non-zero if the channel is currently running. A channel requires service if it is not running and another drive request is queued in software.

3.0: Channel Configuration

Addresses for the control ports for an individual channel are determined as offsets from the channel's base address (which is in turn determined from the board's base address): 
        Offset  R/W  Function
          0      W   Drive In
          2      W   Drive Out
          4     R/W  Current Position
          6      W   Configuration
                 R   Status
Writing a value to the "Drive In" address instructs the channel to drive in the "In" direction by the number of steps specified. Writing a value to the "Drive Out" address has the opposite effect. The drive's "Current Position" is a R/W register, allowing the position to be preset by software, based perhaps on some other sensor's determination of the drive's position. The position can be read "on-the-fly" while the drive is in motion.

Offset 6 is both a write-only configuration port and a read-only status port. The channel is configured by writing the configuration word to offset 6 of the channel's address block. The configuration word is bit-mapped as follows: 

        Bit(s)  Function
          0     Limit Switch Swap
          1     Zero Reference Disable
          2     Step Output Polarity
          3     Direction Output Polarity
          4     Run Output Polarity
          5     Configuration Enable
         8-11   Step Rate Selection
If the Limit Switch Swap bit is zero, the channel's LimitA input is considered to be the InLimit and LimitB is considered to be the OutLimit. If this bit is set to one, the roles of the two switches are reversed. Use of this bit must be coordinated with the setting of the Direction Output Polarity. Both bits must be changed in order to exchange the meanings of "In" and "Out". If the two are not in agreement, the limit switches may be ignored, and the drive motor and/or attached equipment may be damaged. By "in agreement" I don't mean that the configuration bits must be the same value, but simply that when the motor drives out, it is driving toward the out limit and vice-versa. That end can be achieved by either hardware (resoldering the connector) or software (changing the channel configuration) means.

The Zero Reference Disable should be set to one if there is no zero reference hardware for the channel. The zero reference is used to reset the current position to zero the first time the zero reference is observed after driving in to the in limit. If the disable bit is set, the current position is reset to zero at the very beginning of the first drive out after driving in to the in limit.

The step, direction, and run output polarity bits allow optional inversion of the digital signals output to the stepper motor driver. Changing the polarity of the direction signal, for example, redefines which way the motor will turn during a drive in the "Out" direction. Since the stepper drivers are edge-sensitive, changing the polarity of the step output signal will change the phase of the steps relative to the run output. This may be totally insignificant, since every step from this board has both a positive and negative edge.

When setting any of the lower 5 configuration bits, bit 5 must be set also. If a configuration word is written out with bit 5 set to zero, the lower 5 configuration bits will be unaffected and only the stepping rate will be programmed. This is in order to allow easy modification of the step rate without changing the basic configuration, which shouldn't change once the board is configured.

4.0: Rate Selection

The stepping rate is configurable separately for each channel by use of channel configuration bits 8-11. 
        Bits 11-8  Rate
          0000      53
          0001      80
          0010     107
          0011     160
          0100     267
          0101     400
          0110     533
          0111     800
          1000    1067
          1001    1600
          1010    2133
          1011    3200
          1100    5333
          1101    8000
          1110   10667
          1111   16000

5.0: Channel Status

Reading from offset 6 returns the channel status byte: 
        Bit  Definition
        0    In Limit Switch
        1    Out Limit Switch
        2    Direction In
        3    Running
        4    Stat A
        5    Stat B
        6    Zero Reference
        7    Undefined
The In Limit and Out Limit bits are set to 1 when the corresponding limit switch is engaged. The Direction bit is set to 1 whenever the current or previous drive was in the "Out" direction. The Running bit is set to 1 while the channel is actively stepping. Stat A, Stat B and Zero Reference all pass on the values from the drive connector.

6.0: Basic Architecture

Indxr64 supports (n) separate channels. Each channel can be independently configured. The channel includes a 16-bit up/down position counter and a 16-bit drive counter. The up/down counter records the current position by keeping track of steps in the In/down and Out/up directions. The drive counter is used to program the channel to produce a particular number of steps. The position may be automatically cleared by a zero reference input as described in the channel section below. A single write to a channel initiates a drive sequence. The address written to determines whether the drive is in the In or Out direction. The data value written is the number of steps to be driven. Hence, writing out a value of one will result in driving one step.

When a drive sequence is initiated, the RUNOUT signal will be asserted on the next RCLK cycle. On each subsequent RCLK cycle, STEPOUT will be asserted until the desired number of steps has elapsed or the corresponding limit switch has been reached. On the following RCLK cycle, RUNOUT will be de-asserted.

7.0: Interrupt Services

When the drive is completed, an interrupt is requested. Indxr64 attaches directly to a single shared interrupt line on the Subbus64 cable. When this interrupt is serviced, the interrupt control program reads from the interrupt acknowledge (INTA) address. Indxr64 is configured to drive one of eight data lines during an INTA sequence. It will drive a logic 1 on that data line if any of its channels requires service.

If the Indxr64 indicates it requires service, the interrupt request will be passed from the interrupt control program to the indexer control program. The indexer control program will then read from the Indxr64 status address to determine which channels require service. The status address returns one bit for each channel which is the current state of that channels RUNNING signal. A channel requires service if it is not RUNNING and if there is a pending software request for that channel.

last updated: Mon Oct 15 14:11:54 2001 webmaster@huarp.harvard.edu
Copyright 2001 by the President and Fellows of Harvard College
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