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Pin | Signal | Link To |
---|---|---|
1 | GND | U1IDX0.10 |
2 | $1N124(IDX0) | U8IDX0.J18 |
3 | $1N117(IDX0) | U8IDX0.K18 |
4 | $1N123(IDX0) | U8IDX0.K17 |
5 | $1N118(IDX0) | U8IDX0.L18 |
6 | $1N122(IDX0) | U8IDX0.L17 |
7 | $1N119(IDX0) | U8IDX0.M18 |
8 | ~INLIMIT_SP4 @ 0x50 | Z1IDX0.8 |
9 | $1N120(IDX0) | U8IDX0.N18 |
10 | GND | U1IDX0.19 |
11 | ~OUTLIMIT_SP4 @ 0x51 | Z1IDX0.9 |
12 | $1N121(IDX0) | U8IDX0.M17 |
13 | ZEROREF_SP4 @ 0x56 | Z1IDX0.7 |
14 | ENABLE_SP4 @ 0x53 | J4PC.71 |
15 | KILL_A_SP4 @ 0x54 | Z1IDX0.5 |
16 | DIR_SP4 @ 0x52 | J4PC.70 |
17 | KILL_B_SP4 @ 0x55 | Z1IDX0.3 |
18 | STEP_SP4 @ 0x58 | J4PC.68 |
19 | GND | U2IDX0.1 |
20 | ICC_5V | U2IDX0.20 |
Pin | Signal | Link To |
---|---|---|
1 | GND | U2IDX0.10 |
2 | $1N116(IDX0) | U8IDX0.B18 |
3 | $1N108(IDX0) | U8IDX0.C18 |
4 | $1N114(IDX0) | U8IDX0.D18 |
5 | $1N109(IDX0) | U8IDX0.E18 |
6 | $1N113(IDX0) | U8IDX0.F18 |
7 | $1N110(IDX0) | U8IDX0.G18 |
8 | ~INLIMIT_SP3 @ 0x40 | Z2IDX0.8 |
9 | $1N111(IDX0) | U8IDX0.H18 |
10 | GND | U2IDX0.19 |
11 | ~OUTLIMIT_SP3 @ 0x41 | Z2IDX0.9 |
12 | $1N112(IDX0) | U8IDX0.H17 |
13 | ZEROREF_SP3 @ 0x46 | Z2IDX0.7 |
14 | ENABLE_SP3 @ 0x43 | J4PC.58 |
15 | KILL_A_SP3 @ 0x44 | Z2IDX0.5 |
16 | DIR_SP3 @ 0x42 | J4PC.57 |
17 | KILL_B_SP3 @ 0x45 | Z2IDX0.3 |
18 | STEP_SP3 @ 0x48 | J4PC.55 |
19 | GND | U3IDX0.1 |
20 | ICC_5V | U3IDX0.20 |
Pin | Signal | Link To |
---|---|---|
1 | GND | U3IDX0.10 |
2 | $1N99(IDX0) | U8IDX0.A10 |
3 | $1N107(IDX0) | U8IDX0.A11 |
4 | $1N101(IDX0) | U8IDX0.A12 |
5 | $1N106(IDX0) | U8IDX0.A13 |
6 | $1N102(IDX0) | U8IDX0.A14 |
7 | $1N105(IDX0) | U8IDX0.A15 |
8 | ~INLIMIT_SP2 @ 0x30 | Z3IDX0.8 |
9 | $1N104(IDX0) | U8IDX0.A17 |
10 | GND | U3IDX0.19 |
11 | ~OUTLIMIT_SP2 @ 0x31 | Z3IDX0.9 |
12 | $1N103(IDX0) | U8IDX0.A16 |
13 | ZEROREF_SP2 @ 0x36 | Z3IDX0.7 |
14 | ENABLE_SP2 @ 0x33 | J4PC.45 |
15 | KILL_A_SP2 @ 0x34 | Z3IDX0.5 |
16 | DIR_SP2 @ 0x32 | J4PC.44 |
17 | KILL_B_SP2 @ 0x35 | Z3IDX0.3 |
18 | STEP_SP2 @ 0x38 | J4PC.42 |
19 | GND | U4IDX0.1 |
20 | ICC_5V | U4IDX0.20 |
Pin | Signal | Link To |
---|---|---|
1 | GND | U4IDX0.10 |
2 | $1N224(IDX0) | U8IDX0.B3 |
3 | $1N217(IDX0) | U8IDX0.A3 |
4 | $1N223(IDX0) | U8IDX0.A4 |
5 | $1N218(IDX0) | U8IDX0.A5 |
6 | $1N222(IDX0) | U8IDX0.A6 |
7 | $1N219(IDX0) | U8IDX0.A7 |
8 | ~INLIMIT_SP1 @ 0x20 | Z4IDX0.8 |
9 | $1N220(IDX0) | U8IDX0.A9 |
10 | GND | U4IDX0.19 |
11 | ~OUTLIMIT_SP1 @ 0x21 | Z4IDX0.9 |
12 | $1N221(IDX0) | U8IDX0.A8 |
13 | ZEROREF_SP1 @ 0x26 | Z4IDX0.7 |
14 | ENABLE_SP1 @ 0x23 | J4PC.31 |
15 | KILL_A_SP1 @ 0x24 | Z4IDX0.5 |
16 | DIR_SP1 @ 0x22 | J4PC.30 |
17 | KILL_B_SP1 @ 0x25 | Z4IDX0.3 |
18 | STEP_SP1 @ 0x28 | J4PC.28 |
19 | GND | U5IDX0.1 |
20 | ICC_5V | U5IDX0.20 |
Pin | Signal | Link To |
---|---|---|
1 | GND | U5IDX0.10 |
2 | $1N216(IDX0) | U8IDX0.H1 |
3 | $1N208(IDX0) | U8IDX0.H2 |
4 | $1N214(IDX0) | U8IDX0.G1 |
5 | $1N209(IDX0) | U8IDX0.F1 |
6 | $1N213(IDX0) | U8IDX0.E1 |
7 | $1N210(IDX0) | U8IDX0.D1 |
8 | ~INLIMIT_GV @ 0x10 | Z5IDX0.8 |
9 | $1N211(IDX0) | U8IDX0.B1 |
10 | GND | U5IDX0.19 |
11 | ~OUTLIMIT_GV @ 0x11 | Z5IDX0.9 |
12 | $1N212(IDX0) | U8IDX0.C1 |
13 | ZEROREF_GV @ 0x16 | Z5IDX0.7 |
14 | ENABLE_GV @ 0x13 | J4PC.18 |
15 | KILL_A_GV @ 0x14 | Z5IDX0.5 |
16 | DIR_GV @ 0x12 | J4PC.17 |
17 | KILL_B_GV @ 0x15 | Z5IDX0.3 |
18 | STEP_GV @ 0x18 | J4PC.15 |
19 | GND | U6IDX0.1 |
20 | ICC_5V | U6IDX0.20 |
Pin | Signal | Link To |
---|---|---|
1 | GND | U6IDX0.10 |
2 | $1N199(IDX0) | U8IDX0.P1 |
3 | $1N207(IDX0) | U8IDX0.N2 |
4 | $1N201(IDX0) | U8IDX0.N1 |
5 | $1N206(IDX0) | U8IDX0.M2 |
6 | $1N202(IDX0) | U8IDX0.M1 |
7 | $1N205(IDX0) | U8IDX0.L1 |
8 | ~INLIMIT_TV @ 0x0 | Z6IDX0.8 |
9 | $1N204(IDX0) | U8IDX0.J1 |
10 | GND | U6IDX0.19 |
11 | ~OUTLIMIT_TV @ 0x1 | Z6IDX0.9 |
12 | $1N203(IDX0) | U8IDX0.K1 |
13 | ZEROREF_TV @ 0x6 | Z6IDX0.7 |
14 | ENABLE_TV @ 0x3 | J4PC.5 |
15 | KILL_A_TV @ 0x4 | Z6IDX0.5 |
16 | DIR_TV @ 0x2 | J4PC.4 |
17 | KILL_B_TV @ 0x5 | Z6IDX0.3 |
18 | STEP_TV @ 0x8 | J4PC.2 |
19 | GND | U7IDX0.5 |
20 | ICC_5V | U7IDX0.7 |
Pin | Signal | Link To |
---|---|---|
1 | XCHK9(IDX0) | U8IDX0.U3 |
2 | XCHK6(IDX0) | U8IDX0.V1 |
3 | XCHK10(IDX0) | U8IDX0.V18 |
4 | XCHK8(IDX0) | U8IDX0.U17 |
5 | GND | U8IDX0.C7 |
7 | ICC_5V | U7IDX0.8 |
8 | ICC_5V | U8IDX0.D3 |
[IDX0] [Components] [Master] [Signals] [Check]
Connector pin assignments by
Terry Allen.
Web listings compiled using Nets
software on Tue May 1 23:18:14 2001
Copyright 2001 by the President and Fellows of Harvard College