SYSCON104: System Controller Board Spec. Rev 1

Contents:

1. General Information
2. Features
3. Schematic Descriptions
4. Operation
5. Testing

The following is a physical and functional description of all components of the new PC-104 compliant Lightweight (LTWT) System Controller board: x23-7028. (The "x" stands for experimental Xilinx FPGA implementation).

General Information:

The LTWT system controller provides an interface between the ISA bus of the PC-104 motherboard (i.e. The Ampro CoreModule 486) and the ICC Backplane. It will also be the foundation for the new stackthrough ICC bus, which will, in the future, replace the existing ICC backplane. This architecture still allows a 56-pin cable to connect to the ICC backplane.

The following is an address map usage table:

Address (hex)      R/W      Description                                 

   308-309         R/W      ICC Data Port                               

   30A-30B         R/W      ICC Address Port                            

   30C-30D         R/W      Control Port                                

   30E-30F          R       Read-back Option (TBI)                      

     310            W       Global FPGA Reset                           

     311            W       Disarms the Reset circuit and resets        
                            CMDENBL, LOWPOWER, and SYSRESET.            

   312-313         R/W      Configuration Port A                        

   314-315         R/W      Configuration Port B (Board and Software    
                            Rev number)                                 

     316            R       General purpose Input Port                  
                    W       Power Fail  IRQ Enable clear                

     317            W       Output Lamps                                

     318            W       Sets CMDENBL to value of D0                 

     319            W       TICK                                        

     31A           R/W      Write Program frame to FPGA                 
                            Read program status (busy/ready)            

     31B            W       Re-program FPGA Command (Set PM=H)          

     31C            R       Error checking port during configuration    

Features:

• SUBBUS Address/Data for R/W with Acknowledge
• Command Strobe
• CMDENBL/fail-safe timer/system reset
• 8-bit input for reading front panel switches
• Power Failure and Spare IRQ
• LED status indicators
• Software configurable board and IRQ options
• Software or hardware re-programmability
• Software controlled reset and re-program commands

Options:

• Experiment IRQ port, sense and enable
• Power Fail IRQ port and enable
• Spare IRQ port and enable
• Auto EXPWR! on ICC Data Write

The controller board contains a Xilinx XC4005A FPGA device that is programmed automatically upon power-up. Depending on the length of the program this could take up to 2.8ms max. (420µs min.). If necessary, the FPGA can also be programmed by the computer by writing the programming strings to address port 31Ah.

Schematic Descriptions:

The MAIN schematic represents the PC board level schematic. Within it are components that contain further schematics (e.g. BRAINS, GLUE) some of which contain further hierarchy levels within them. The following figure shows a schematic hierarchy tree (in the x23_7028 project unless noted):

Main

This is the main printed circuit board schematic. P1 and P2 represent the PC/104 AT bus connectors. J1 is the PC/DP connector (40 pin according the appended February 8 1995 definition). J2 is the SUBBUS connector (64 pins following the appended February 8 1995 definition). The contents of GLUE and BRAINS will be explained later. The XC17128 (U11) is the Xilinx Serial PROM. It contains the bitstream that will be downloaded onto the FPGA upon power-up or command from the computer. The IRFD020 (Q1) will drive a system reset on command from the RESET_BUTTON signal. This is similar to pressing the Reset button on the computer itself.

A watchdog timer and power monitoring IC resides on board. U10, the Linear technology LTC690 (or equivalent:LTC694, MAX694) will take a watchdog timer input on the WDI pin. This signal must be repeated at intervals of less than 1.6 seconds or a reset signal will be issued on the RESET! line. The INA111 (U12) circuit resolves the isolation problem between the DIGGND and the 28VRET (system power ground), for the power fail option. The 28v power is sampled via a voltage divider so that the INA111 will issue a PFO! (Power Fail Out) as soon as the power starts decays below 20 v. Jumper JP2 serves as a test port for the power fail circuit. Momentarily shorting JP2 should trigger U12, and make U10 issue a PFO.

JP6 and JP7 are IRQ inputs to the BNCIRQ and the SPRIRQ signals respectively. E4 through E7 and JP5 are all spare connections to extra pins on the FPGA. JP5 is connected to the TDO signal which is used in boundary scan functions. JP3 selects the kind of termination power applied on the resistor networks: 1-2: Passive (Default); 2-3: Active termination. JP4 selects the buffering option on EXPINTR!: 1-2: bypass buffer; 1-3:2-4 Buffer EXPINTR!.

All de-coupling capacitors are shown together even though they are placed directly below the devices they de-couple. This board also provides room for de-coupling resistors placed in series between power and the Vcc inputs of all 54HC parts to enhance the power supply de-coupling.

All 54HC640 (U3 through U6) octal bus transceivers and the 54HC244 (U7) can be replaced by 54BCT640's and a 54BCT244 respectively. The 220/330 ohm resistor networks (Z3 through Z7) will be installed only when using BCT bus drivers.

Glue

The Altera EPM5032 provides the glue logic necessary between the FPGA and the AT bus when the FPGA is not in a programmed state.

• ADDR[9:0] and IOWR!: AT backplane address bus and IOWR! line.
• CS0! and CS1: Active on signals 31xhDONE! and address xxAh respectively. These signals provide chip addressing values together with IOWR!, during asynchronous peripheral mode programming. Once the FPGA is programmed CS0! is also the Global Reset net into the FPGA.
• PM: The current program mode. True (or high) designates Asynchronous parallel mode, while a false (or low) value would mean Master serial mode (power-up default). PM is set by writing to address 310h.
• AT_RESET: The AT backplane RESET line.
• MAX_RESET!: The output of the Processor Supervisor IC's RESET! signal.
• DONE: Output from the FPGA. Goes true once it has been successfully programmed.
• PROGRAM!: Connects to the PROGRAM! input of the FPGA and commands it to erase the current program and await a new one as dictated by PM.
• PROM_RESET!: Commands the XC17128 Serial PROM to reset and disable its output.
• AT_D0: DATA0 line from the AT backplane.
• X_D0: DATA0 line from the FPGA.
• XIE and XOE!: "Input to" and "output from" the FPGA enables signals. This is how the FPGA commands the data direction through the GLUE logic.
• INIT!: Goes true (low) when the FPGA has been programmed effectively, and all signals are valid. Also signals an error if true when not done programming.

Note that the error checking operation on address 31Ch is not qualified with IORD! (as it should properly be). This could cause glitching on the DATA0 line while the address is not stable. This can (will) be improved.

XC17128-Serial PROM

The Xilinx XC17128 Serial PROM (or the ATT17128 e²SROM for testing) contains the program to be downloaded onto the FPGA upon power-up or on a re-program from ROM command .

Brains

The AT address bus goes into a composite symbol named Address Decode. The schematic and symbol for this part are named ADDRDEC.

ADDRDEC: Provides all the address decoding for the whole schematic. The signals DIO and IOCS16! (which are complements of each other) are generated when any part of the board is addressed.(300h through 31Fh).

the ANNUNC signal can be accessed by addressing 317h or writing to the high byte of address 316h.

A list of the decoded signals is shown below:

 Address (hex)       Signal     Description                                

   308 or 309        Port_A     Enable ICC Data port                       

   30A or 30B        Port_B     Enable ICC Address Port                    

   30C or 30D        Port_C     Enable Control Port                        

   30E or 30F        Port_C     Enable Readback Control Port               

      310             GSR       Global Reset line                          

      311           ARMRESET    Disarms the Reset circuit and resets       
                                CMDENBL, LOWPOWER, and SYSRESET.           

    312-313           CPA       Configuration Port A                       

    314-315           CPB       Configuration Port B (Board and Software   
                                Rev number)                                

      316          INPUTPORT    General purpose Input Port and Power Fail  
                                enable                                     

      317            ANNUNC     Output Lamps                               

      318          CMDENBLSEL   Sets CMDENBL to value of D0                

      319           TICKSEL     TICK                                       

300 through 31F      DIO or     Enables the I/O buffers for D0 in GLUE     
                    IOCS16!                                                

IRQ MNGR: The IRQ Manager curcuit routes the correct interrupt signals to their corresponding interrupt request lines.

2 min. TIMER: A 2 minute timer to provide an output lamp if the computer does not turn on and issue a TICK within two minutes of power-up. The timer is constructed of an 11-bit Linear Feedback Shift Register pseudo-random counter (C11LFSR schematic), to avoid the possibility of spiking on the output.

Signals definitions:

• DATA_BUS: Internal Data Bus. Same as AT Data bus if DIO Is true.
• Control Port: This is a collection of signals from different areas of the circuit. It is adressable at 30Ch-30Dh, and it is used for diagnostic and debugging purposes. The following signals are part of this bus:

 Port C    R/W          Signal         
   bit                                 

   12       R            PFO!          

   11       R       EXPRD + EXPWR      

   10       R          LOWPOWER        

    9       R         CMDENBL/!        

    8       R     EXPACK! (current)    

    6       R    EXPACK (at Timeout)   

    5      R/W     ICC_5V / BUF_OE     

    4       W   BUF_OE! Modify Enable  

    3       W      CMDSTRB! Modify     
                        Enable         

    2       W           EXPWR          

    1       W          CMDSTRB!        

    0       W           EXPRD          

ICCDATA: Internal ICC Data bus. Addressable at 308h-309h.

• ICCADDR: Internal ICC Address bus. Addressable at 30Ah-30Bh.
• XIE, XOE!: Enabled by DIO (ADDRDEC) and qualified by IORD these signals, which are identical during normal operation of the XC4005A FPGA, enable or disable the buffers on DATA0 in GLUE.
• CMDENBL: The PC/ICC architecture specifies that all discrete commands emanating from the ICC be qualified not only by the command strobe, but also by a command enable signal. The purpose of this signal is to lessen the possibility that the computer will issue erroneous commands while it is in the process of crashing.

How do we know if the computer is qualified to issue commands? The system controller board features a fail-safe timer which is capable of resetting the computer in the event of a software or hardware malfunction which interrupts normal operation. The timer is activated by writing to the TICK address (319h). Once the timer is activated, a TICK must be written every second or the board will issue a hardware reset. The CMDENBL signal may be set or reset under software control by writing 1 or 0 (on D0) to address 318h, but it is enabled onto the backplane only when the fail-safe timer is activated. The timer may be deactivated by writing to address 311h. This not only disarms the fail-safe timer but also resets CMDENBL so that it must be explicitly re-enabled if the timer is reactivated.

For diagnostic purposes the CMDENBL/! signal which appears on the ICC backplane may be read on bit 9 of the Control port (PORT_C; address 30Eh)

• TICK: Qualified by IOWR, sets ARM high, which enables the CMDENBL/! signal. Also resets the 2 min. timer and issues a watchdog input signal to the Processor Supervisor IC.
• SICDISABLE: Resets CMDENBL, the power-fail IRQ, and the ARM circuit on a write to address 311h (ARMRESET), or a system reset occurs (SYSRESET! goes true).
• RESET!: Issued by the Processor Supervisor IC, causes a system reset on SYSRESET if ARM'ed.
• LOWPOWER: Power Fail IRQ issued by the Supervisor IC when power falls below threshold. This signal; is available on bit 10 of the control port. (30Ch).
• CP_A, CP_B: Configuration Ports A and B control several of the functions on the FPGA, and are both 16-bit readable and writable registers at addresses 312h and 314h respectively. See below for the function definition of each bit:

 Control Port   Default     Signal                   Purpose                 
     Net                                                                     

   CPA[2:0]       000       EXPIRQ    Experiment IRQ Select                  

     CPA3          0        EXPIRQ    EXPIRQ Source Select                   

     CPA4          0        EXPIRQ    BNCIRQ Sense                           

     CPA5          0         E12A     EXPIRQ Enable                          

   CPA[8:6]       101        PFIRQ    Power Failure IRQ Select               

     CPA9          0          JP4     PFIRQ Enable                           

  CPA[12:10]      110        SPIRQ    Spare IRQ Select                       

    CPA13          0                  Spare IRQ Enable                       

    CPA14          1                  Auto EXPWR! on ICCDATA Write Enable    

    CPA15          1                  Timeout Enable                         

  CPB[15:0]      4B01h         -      Board and LCA  software revision       
                                      number Information.  (Format TBA)      

NOTE: JP3, JP2 and JP4B have been removed from the board

• CMDSTRB!: Global ICC Command Strobe signal, issued by writing a 1 to the Control Port (PORT_C) at address 30Ch.
• EXPRD!, and EXPWR!: ICC control signals issued by writing a 0 or 2 to the Control Port at address 30Ch.
• TIMEOUT: Goes high about 1second after EXPRD! or EXPWR! is issued. It resets the EXPRD! or EXPWR! signal and latches the data at the ICC Data input, and the value of EXPACK!. The clock source can be the internal oscillator to the XC4005A or the AT bus clock, selectable via CP_A13.
• EXPACK!: ICC issued acknowledge that an ICC address or a piece of ICC data was received by the ICC. It gets latched on TIMEOUT and can be read on the Control Port (31Ch).
• INPUT PORT: 8-bit general purpose Input Port. Accessible at address 3316h.
• LAMPS: Outputs to eight status lamps on the cockpit. LAMP0 turns on if the 2 minute time-out expires, signaling a computer malfunction.
• IRQSEL: Four different IRQ are OR'ed together into one of eight different IRQ options. Un-selected IRQ's are not driven (tri-stated). The IRQ selection and enabling is made through configuration port A. The Available IRQ's are as follows:

 IRQSEL bit    AT IRQ    

  IRQSEL7       IRQ9     

  IRQSEL6       IRQ3     

  IRQSEL5       IRQ4     

  IRQSEL4       IRQ5     

  IRQSEL3       IRQ6     

  IRQSEL2       IRQ7     

  IRQSEL1       IRQ10    

  IRQSEL0       IRQ11    

Operation

On power-up, the EPLD (U2) will set PM to the default low level. This will select a Master Serial Mode on the FPGA which will automatically download its contents from the Serial PROM. Once programmed (2.8ms max.), it will begin timing the 2 minutes to make sure the computer comes up. If not, LAMP0 will be asserted, otherwise, TICK will start ticking the Processor Supervisor IC, and arming the ICC command path. The ICC Read and Write commands are asserted in the following manner:

Write Cycle

1. Write the SUBBUS address to the ICC address port.
2. Write the data value to the ICC data port. (This automatically issues an EXPWR! on the control port)
3. Wait for TIMEOUT (1second) to latch EXPACK!, and to reset EXPWR!
4. Check for EXPACK! by reading the Control port.

Read Cycle

1. Write the SUBBUS address to the ICC address port.
2. Issue an EXPRD! on the control port.
3. Wait for TIMEOUT (1second) to latch EXPACK!, and to reset EXPRD!
4. Read data from the ICC Data port and check for EXPACK! by reading the Control port.

A read or write cycle is considered successful if we have an EXPACK! at the end of the routine.

Testing

A test suite will be compiled and made standard for all controller board versions. We intend to read from the ICC Address bus to find out what version board and software revision exist in the system. This read operation would actually read the contents of configuration port B on one of the latest boards.