SYSCON104 Notes

• Assembly Issues
• Connector Dispositions
• Jumpers and Resistor Networks
• Assembly Mods
• Revision History

Assembly Issues

Connector dispositions

All four connectors are subject to modification depending on the configuration of the target system.

J1

It is safe to say that J1 should be a simple vertical connector (pins up). Originally, we thought it should be a right angle, but that tends to interfere with nearby components. The downside is that the connection must generally be made before any additional components are stacked above the system controller.

J2

J2 can either be a stack-through connector or a simple socket. If the stack is right-side-up (PC-104 on the solder side, SB64 on the component side) the pins are unnecessary and often conflict with components on the board below. If the stack is upside-down, the pins are required as the base of the SB64.

P1

Generally is a stack-through connector. If the stack is going to be used in conjunction with an ISA mini-backplane, and the stack is right-side-up, a connector with long pins on one side for the PC/104 stack and short pins on the other for the extension will work nicely.

P2

Several configurations. On systems with old-style PC/104, P2 was a right-angle connector which was connected by a daisy-chained cable. New-style PC/104 uses the stack-through approach. On new-style systems, the same consideration applies as for P1 regarding connecting to an ISA mini-backplane.

Jumpers and Resistor Networks

JP2: Power Fail Test Jumper

Default: Open. Short to test power fail interrupt.

JP3: Termination Power

Default: 1:2. Jumper 2:3 for Active Termination.

JP4: EXPINTR

Default: 1:2. Jumper 1:3, 2:4 to pass through buffer.

JP5: Spare Jumper

Default: Open

JP6: BNCIRQ

Default: Open

JP7: SPRIRQ

Default: Open

Z3, Z4, Z5, Z6: Termination Resistors for Address/Data

Not installed by default.

Z7: Termination Resistors for Control

Install a 10K sip with pin 10 cut (i.e. make it a pullup instead of pullupdown.)

Z8: Pullup for I/O Switches

Install 10K

Z9: Pulldown for Lamp outputs

Install 10K

Z10: Miscellaneous pullups

Install 10K

Assembly Mods Required

Tie ANAGND to DIGGND

Connect J2-57 to J1-31, J1-29 and J1-27.

J1-27 is the only one of these actually connected to DIGGND on the board. J1-29 should have been. J2-57 and J1-31 are defined as ANAGND, but never made it onto the SYSCON104 schematic.

Tie VBatt to DIGGND

Connect J1-21 to J1-22.

Since we don't use a battery, it is important to keep VBatt below Vcc for normal operation.

Install Pullup 10K in Z7.

Z7 is laid out for termination pullup-pulldown, so we must clip pin 10 on the SIP.

Jumper JP3 1-2.

To define the voltage by which Z7 is pulled up.

Criss-cross R4 and R5

The positive and negative inputs to the INA111 are reversed. This can be resolved by connecting the R4 resistor from R4-1 to R5-2 and the R5 resistor from R5-1 to R4-2. It may make sense to put one resistor on the top of the board and the other on the bottom.

Connect 10K resistor from JP2-1 to (J1-27,29,31)

Must relate 28VRTN to ANAGND/DIGGND

Add .1 uF to C10

Existing .01 is not enough.

Connect J2.37 to JP7.1

This wire connects the unused EXPEN0 pin on the subbus cable to the SPRIRQ pad in order to route interrupts from H2O or Ozone to the computer.

For SYSCON's without EPLD (Glueless)

Version A.1.3 of the SYSCON FPGA doesn't use an EPM5032 EPLD (GLUE) on the board. SPROMs will be labeled "rA3" for rev.A.1.3 (abbreviated for lack of room on label)

Other markings on the SPROM label, such as "xA." signify that the version is for an XC4005A FPGA.

Remove EPLD, and either remove or block socket so nothing can be plugged in

Connect PROM_RESET\ to PROGRAM\

Tie U2.13 to U2.27 on EPLD

Add 10K Pullup to PROGRAM\ pin

Tie U2.13 or U2.27 on EPLD (from above) to Z10.8

Connect AT_DATA0_IN to CS0\ on FPGA (U1.P10)

Tie U2.12 to U2.4 on EPLD

Connect PM to DIG_GND (Program pins set for Mater Serial)

Tie U2.2 to U2.28 on EPLD

Add 10K Pullup to DONE pin

Tie U2.10 on EPLD to Z10.9

Add a Jumper for SYSCON Adressing starting at 0320H (Optional)

2-pin Jumper between U2.2 (DIG_GND after preceding mod is completed) to U2.3 on EPLD

Internal Changes

Lamp register should not clear on MAX_RESET/.

We could either clear it on SYS_RESET_/ or not at all.

Replace RESET/ circuit with an inverter.

Use ARM to enable the WDI output. When disarmed, WDI will float, disabling the Watchdog feature of the LTC690. This simplifies this circuit and allows low-power resets to pass through the Xilinx part.

Revision History

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