SB/64 Ungated Counters

• Addressing
• Status Word
• Operation
• Initialization

• 600 Status Word
• 602 Hardware Rev
• 610 Counter 1 Low Word
• 612 Counter 1 High Word
• 614 Counter 2 Low Word
• 616 Counter 2 High Word
• 618 Counter 3 Low Word
• 61A Counter 3 High Word
• 61C Counter 4 Low Word
• 61E Counter 4 High Word

• D0 Counter 1 Overflow
• D1 Counter 2 Overflow
• D2 Counter 3 Overflow
• D3 Counter 4 Overflow
• D4 Counter 1 16-bit Overflow
• D5 Counter 2 16-bit Overflow
• D6 Counter 3 16-bit Overflow
• D7 Counter 4 16-bit Overflow
• D8-D11 Integration Period
• F == 1 Hz
• 7 == 2 Hz
• 3 == 4 Hz
• 1 == 8 Hz
• 0 == 16 Hz
• D12 Counter 1 1=ungated 0=complimentary
• D13 Counter 2 1=ungated 0=complimentary
• D14 L2Stat
• D15 Resynch

The counters are automatically synchronized with reads of the status word, but in order for this to work reliably, we need to take steps to make sure the status and the counters are read in the correct order and close together in time. i.e. we need to use a TM group to collect the counters:

    %{
      #define CT24long(x) ((long)(x).low + (((long)(x).high)<<8))

      TM typedef struct {
        unsigned short low;
        unsigned char high;
      } CT24 { convert long CT24long(); }
      TM CT24 4 Hz DetA;
      TM CT16 4 Hz DetB, DetC, DetD;

      Group Cts ( CtStat, DetA, DetB, DetC, DetD ) {
        CtStat = sbwa( CtStat.address );
        DetA.low =  sbwa( DetA.address );
        DetA.high = sbba( DetA.address+2 );
        DetB = sbwa( DetB.address );
        DetC = sbwa( DetC.address );
        DetD = sbwa( DetD.address );
      }
    %}

Initialization:

The counters must be programmed initially to set the integration period. This must match the reporting rate.

      %{
        #define DG_CUSTOM_INIT Ct64_init()
        static void Ct64_init( void ) {
          sbwr( 0x600, 0x0300 ); /* HCtr 4 Hz */
          sbwr( 0x640, 0x0300 ); /* NCtr 4 Hz */
        }
      %}