Analog I/O Board

Contents:

1. General Description
2. Features
3. SUBBUS64 Interface
4. A/D Section
5. D/A Section
6. High Resolution A/D Serial Interface
7. Address Map

General Description:

The Analog I/O board (ANAIO64) allows our Data Acquisition system to record and generate analog signals from and to any instrument. It also provides a serial interface for later connection to High Resolution Serial A/D Converter(s).

The following specification documents the characteristics of the SUBBUS64 Analog I/O board

Features:

• 40 Unipolar, 12-bit Resolution Analog Input Channels
• 8 12-bit Analog Output Channels
• Serial Interface to External High Resolution A/D systems
• Asynchronously Read Data
• Hardware/Software Address Selection

SUBBUS64 Interface

This board will support the standard SUBBUS64 64-pin interface: 16-bit Address and Data buses, and 6 control signals. Refer to the System Controller Connector Definition specification for more information.

A/D Section

The board provides 40 unipolar input channels of 12-bit resolution A/D conversion through a set of five AD7890-10. This device is an 8-channel multiplexed, monolithic, Serial, Data Acquisition system. The -10 model accepts analog signals of up to ±10V and allows for filtering and amplification of the signal between the multiplexer and sample and hold stages of the converter.

Each signal is carried into the board as a signal pair all the way to the A/D converters. The low end terminates onto the ANAGND plane near the A/D input pin.

The board generates separate programmable gain amplifier (PGA) and filter settings for each channel; these settings are saved on the on-board FPGA (Xilinx 4000E series device), which also acts as the controller. The results of the conversion will be collected from each A/D for every channel according to the sequence below: (NOTE: The on board FPGA will readily accomodate any architecture changes, should the collection sequence change in any way).

1. Read the current 12-bit value from the AD7890 and save it to dual-ported SRAM on FPGA.
2. Set PGA gain and Filter frequency according to channel requirements.
3. Send next channel number information and Convert command.
4. Repeat for next AD7890, or increment channel number and begin with first AD7890.

D/A Section

The board also provides eight Analog outputs as signal pairs. These are generated via two MAX536 Serial interface Quad D/A converters. A single serial data, clock, and "Load" command (\LDAC) lines connect to both devices, with separate Chip-Selects (\CS1 and \CS2). The DAC outputs will change every time the \LDAC line is asserted. In order to be able to update more than one output at a time, the \LDAC line will only be asserted after a new piece of data is received if the \LDAC-flag bit (bit 15 of the DATA word) is TRUE.

The D/A write cycle is as follows:

1. The computer writes a new 16-bit value (only the least significant 12 bits will be used) to the correct address (see Address Map Section).
2. The value is saved on a shift register and clocked onto the D/A data line. Only the enabled D/A, as determined by the address, will receive the data.
3. Immediately after, if the \LDAC-flag is TRUE, \LDAC will be asserted, loading the input register values onto the DAC registers, changing the analog output voltages.

High Resolution Serial Interface Section

This interface will serve one or more High Resolution A/D's installed near their source. This will reduce the amount of noise associated with carrying low-level signals from the source to the A/D converter. There is address space for eight A/D devices, though more can be multiplexed in if necessary. The interface will resemble the 4-wire AD7890 serial interface

1. SCLK: Serial interface clock.
2. \TFS: Transmit data Frame Synchronization pulse. The assertion of this signal marks the beginning of an incoming serial data frame to the A/D device.
3. \RFS: Receive data Frame Synchronization pulse. Assertion of this pin allows access to the data on the output register.
4. DATA IN/OUT: Serial Data line, used for Input and Output.

Address Map

The address partition for ANAIO boards C00H-DFFH, which give us enough room for eight This will include both A/D, D/A and High Resolution A/D functions.

Address Usage .

C00H - C0FH Status word, Software/Hardware Revision number, miscellaneous switches, etc

C10H - C5FH A/D Channels (40)

C60H - C6FH D/A Channels (8)

C70H - C7FH High Resolution A/D Interface (8)